AArch64 MP+dmb.sy+[fr-dmb.st-rf]-addr
"DMB.SYdWW Rfe FrLeave DMB.STdWW RfBack DpAddrdR Fre"
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T,2:y=F,2:z=W
Com=Rf Fr Rf
Orig=DMB.SYdWW Rfe FrLeave DMB.STdWW RfBack DpAddrdR Fre
{
0:X1=x; 0:X3=y;
1:X1=y; 1:X3=z; 1:X6=x;
2:X1=y; 2:X3=z;
}
P0 | P1 | P2 ;
MOV W0,#1 | LDR W0,[X1] | MOV W0,#2 ;
STR W0,[X1] | LDR W2,[X3] | STR W0,[X1] ;
DMB SY | EOR W4,W2,W2 | DMB ST ;
MOV W2,#1 | LDR W5,[X6,W4,SXTW] | MOV W2,#1 ;
STR W2,[X3] | | STR W2,[X3] ;
exists
(y=2 /\ 1:X0=1 /\ 1:X2=1 /\ 1:X5=0)